The present invention relates to an oscillation circuit, and a semiconductor integrated circuit device which includes a clock distribution system of low jitter and low skew employing the oscillation circuit.
A clock generation method which uses a conventional PLL (Phase-locked loop) is disclosed in, for example, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL 27, NO 11, November 1992 (hereinbelow, referred to as the xe2x80x9cprior art example Axe2x80x9d).
FIG. 2 illustrates the construction of a clock generation unit which employs the conventional PLL. A reference clock signal fext input to the PLL from outside the circuit. The PLL includes the following: xe2x80x9cPFDxe2x80x9d, a phase/frequency comparator; xe2x80x9cCPxe2x80x9d, a charge pump; xe2x80x9cLPFxe2x80x9d, a low-pass filter; xe2x80x9cVOC0xe2x80x9d, a voltage-controlled oscillator; xe2x80x9cDIVNxe2x80x9d, a 1/N frequency divider; xe2x80x9cDIV2xe2x80x9d, a xc2xd frequency divider; and xe2x80x9cN0xe2x80x9d, a clock distribution network. The details of each of these circuit elements is omitted.
The difference between the phases or frequencies of the reference clock signal fext and an internal clock signal fint is compared by the phase/frequency comparator PFD, from which an error signal UP or DN is output. The error signal is converted into an analog signal by the charge pump CP, and the high frequency components of the signal are removed by the low-pass filter LPF. The resulting signal is input to the voltage-controlled oscillator VCO0 as an oscillation-frequency control signal VC. The oscillation output of the voltage-controlled oscillator VCO0 is divided by the frequency divider DIV2 into an oscillation output fint0 whose frequency is half the frequency of the former oscillation output and whose duty ratio is 50%, and which is input to the clock distribution network N0.
The return signal fint from the clock distribution system has its frequency divided by the 1/N frequency divider DIVN. The resulting signal is input to the phase/frequency comparator PFD. The phases of the reference clock fext and internal clock fint are locked by such a phase-locked loop PLL0, and the frequency of the signal fint becomes N times that of the signal fext.
The frequency of the internal clock fint has increased year by year, and the area of the clock distribution network N0 has been enlarged in accordance with increases in chip area. Problems occur in a clock distribution system when the clock is to be stably fed at high speed over a wide area. Such problems, as mentioned below, occur with the prior art Example A.
(1) The delay time of the clock distribution network, that is, the delays in the signals fint0 and fint, become(s) relatively long in comparison with 1/fint. Thus, the skew of the clock distribution network influences the performance of the whole clock distribution system into which the clock distribution network and the phase-locked loop PLL0 are combined. Also, there is a method wherein a clock feed range within a chip is split in a large number, and wherein independent PLLs are provided for the respective clock feed subranges. In the case of this method, however, problems as mentioned below are involved.
(2) In general, a PLL is less immune to noise such as power source noise and substrate noise, and such noise increases the xe2x80x9cjitterxe2x80x9d of the oscillation frequency and phase of the signal fint0. The provision of the large number of PLLs within the chip leads to the necessity of considering noise reduction for each of the PLLs.
(3) The total area of the large number of PLLs affects the area of the entire chip. In consideration of the problem (2), the area of each of the PLLs increases even more.
(4) The clock skew between the independent clock feed subranges becomes as very large as TskewG+2*TskewL+2*Tjitter, where TskewL denotes a skew within the respective clock feed subranges, Tjitter denotes the jitter of the PLLs, and TskewG denotes the skew of the reference clock having occurred up to each PLL.
(5) Since the PLLs are provided in such a large number, dissipation power increases.
The objects of the invention are to solve the aforementioned problems by providing an oscillation circuit and a semiconductor integrated circuit device which includes a clock distribution system using the oscillation circuit.
In particular, it is an object of the invention to provide a semiconductor integrated circuit device having a plurality of oscillators each having an oscillation node, wherein the oscillation nodes of each of the oscillators are connected together. Preferably, the oscillators are connected together by conductive wiring line that may be a closed loop.
It is a further object of the invention that the oscillators are synchronized to oscillate at substantially the same frequency and further to oscillate at substantially the same phase.
It is another object of the invention that the oscillators are connected to a wiring at connecting points having substantially the same interval of wiring lengths between the connection points, which leads to synchronizing the oscillators to oscillate at a substantially identical frequency and phase.
In a preferred embodiment of the invention, the semiconductor integrated circuit device has a plurality of oscillators that are connected to a conductive wiring line that is formed in the shape of a mesh, at the intersection points of the mesh, wherein the interval of length of the conductive wiring line between the connection points is substantially the same among all of the connection points. Preferably, the interval length is at least 50 xcexcm.
In a further object of the present invention, the oscillators are ring oscillation circuits having inverters connected in a ring shape wherein an output of at least one inverter of each ring oscillation circuit is connected to the conductive wiring. Alternatively, the oscillators may be delay lines having multistage connected inverters with at least one inverter connected to the conductive wiring line.
According to another object of the invention, a semiconductor integrated circuit device is provided with a plurality of circuit blocks having a clock distribution circuit and a plurality of oscillators that output a clock signal to the clock distribution circuit in which a conductive wiring is provided for connecting oscillation nodes of each of the oscillators together. In such an arrangement, the circuit blocks may comprise a logic circuit or a memory circuit and the plurality of oscillators may be provided in one-to-one correspondence with the plurality of circuit blocks.
In still another object of the invention, a semiconductor integrated circuit device has a plurality of oscillation circuits with a wiring connecting the output of oscillation circuits together, a plurality of clock distribution circuits that are connected to the oscillation circuits and a phase frequency converter that compares the clock signal of the clock distribution circuits with a reference clock signal wherein the oscillation circuits change in oscillation frequency in response to a signal output from a phase frequency comparator.
According to the present invention, a semiconductor integrated circuit device is provided having a plurality of oscillators having substantially the same natural oscillation frequency and a conductive wiring that connects the outputs of each of the oscillators together. As a result, the oscillators oscillate at substantially the same frequency independently of fluctuations in the supply of voltage to each of the oscillators. Further, since the oscillators are synchronized to provide substantially the same output frequency which is independent of fluctuations in the supply voltages, the oscillators are suitable for providing a clock signal to a plurality of clock distribution circuits that distribute clock signals to circuit blocks on the semiconductor integrated circuit device. As a result, a clock signal is provided that is distributed according to the preferred embodiments of the invention that is not subject to variations due to noise and therefore has low jitter and skew.